X-Git-Url: http://j8takagi.net/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=test%2Fintegration%2Fcasl2%2Fcmd_SRA_sra_z%2F0.txt;fp=test%2Fintegration%2Fcasl2%2Fcmd_SRA_sra_z%2F0.txt;h=1c369241879723b1fa90ccb8587321549c288a8c;hb=e53b9aa2cd0e67ff64c52fa1b83e16c048283dbd;hp=0000000000000000000000000000000000000000;hpb=f2b4a9880e544d2fcb54f5a6dda673f67767d93d;p=YACASL2.git

diff --git a/test/integration/casl2/cmd_SRA_sra_z/0.txt b/test/integration/casl2/cmd_SRA_sra_z/0.txt
new file mode 100644
index 0000000..1c36924
--- /dev/null
+++ b/test/integration/casl2/cmd_SRA_sra_z/0.txt
@@ -0,0 +1,63 @@
+../../../../casl2 -atd -M8 ../../../../as/cmd/SRA/sra_z.casl
+
+Assemble ../../../../as/cmd/SRA/sra_z.casl (0)
+
+Assemble ../../../../as/cmd/SRA/sra_z.casl (1)
+../../../../as/cmd/SRA/sra_z.casl:    1:;;; SRA r,adr 結果は零
+../../../../as/cmd/SRA/sra_z.casl:    2:MAIN    START
+../../../../as/cmd/SRA/sra_z.casl:    3:        LAD     GR1,#2000
+	#0000	#1210
+	#0001	#2000
+../../../../as/cmd/SRA/sra_z.casl:    4:        SRA     GR1,15
+	#0002	#5110
+	#0003	#000F
+../../../../as/cmd/SRA/sra_z.casl:    5:        RET
+	#0004	#8100
+../../../../as/cmd/SRA/sra_z.casl:    6:        END
+
+Executing machine codes
+#0000: Register::::
+#0000: GR0:      0 = #0000 = 0000000000000000
+#0000: GR1:      0 = #0000 = 0000000000000000
+#0000: GR2:      0 = #0000 = 0000000000000000
+#0000: GR3:      0 = #0000 = 0000000000000000
+#0000: GR4:      0 = #0000 = 0000000000000000
+#0000: GR5:      0 = #0000 = 0000000000000000
+#0000: GR6:      0 = #0000 = 0000000000000000
+#0000: GR7:      0 = #0000 = 0000000000000000
+#0000: SP:       8 = #0008 = 0000000000001000
+#0000: PR:       0 = #0000 = 0000000000000000
+#0000: FR (OF SF ZF): 000
+#0000: Memory::::
+#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+#0000: 0000: 1210 2000 5110 000F 8100 0000 0000 0000 
+#0002: Register::::
+#0002: GR0:      0 = #0000 = 0000000000000000
+#0002: GR1:   8192 = #2000 = 0010000000000000
+#0002: GR2:      0 = #0000 = 0000000000000000
+#0002: GR3:      0 = #0000 = 0000000000000000
+#0002: GR4:      0 = #0000 = 0000000000000000
+#0002: GR5:      0 = #0000 = 0000000000000000
+#0002: GR6:      0 = #0000 = 0000000000000000
+#0002: GR7:      0 = #0000 = 0000000000000000
+#0002: SP:       8 = #0008 = 0000000000001000
+#0002: PR:       2 = #0002 = 0000000000000010
+#0002: FR (OF SF ZF): 000
+#0002: Memory::::
+#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+#0002: 0000: 1210 2000 5110 000F 8100 0000 0000 0000 
+#0004: Register::::
+#0004: GR0:      0 = #0000 = 0000000000000000
+#0004: GR1:      0 = #0000 = 0000000000000000
+#0004: GR2:      0 = #0000 = 0000000000000000
+#0004: GR3:      0 = #0000 = 0000000000000000
+#0004: GR4:      0 = #0000 = 0000000000000000
+#0004: GR5:      0 = #0000 = 0000000000000000
+#0004: GR6:      0 = #0000 = 0000000000000000
+#0004: GR7:      0 = #0000 = 0000000000000000
+#0004: SP:       8 = #0008 = 0000000000001000
+#0004: PR:       4 = #0004 = 0000000000000100
+#0004: FR (OF SF ZF): 001
+#0004: Memory::::
+#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+#0004: 0000: 1210 2000 5110 000F 8100 0000 0000 0000