X-Git-Url: http://j8takagi.net/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=test%2Fsystem%2Fcasl2%2Fcmd_cpl_r_adr__z%2F0.txt;fp=test%2Fsystem%2Fcasl2%2Fcmd_cpl_r_adr__z%2F0.txt;h=9d3600688d6e7a97b70db9e8af4f65b85541601e;hb=66e1d81600e0a66998245b5d11a75ccf30886ab6;hp=0000000000000000000000000000000000000000;hpb=9e662b933c41f16c22598248b8aefe7c8efb4c88;p=YACASL2.git

diff --git a/test/system/casl2/cmd_cpl_r_adr__z/0.txt b/test/system/casl2/cmd_cpl_r_adr__z/0.txt
new file mode 100644
index 0000000..9d36006
--- /dev/null
+++ b/test/system/casl2/cmd_cpl_r_adr__z/0.txt
@@ -0,0 +1,74 @@
+;;; CPL r,adr ZF:0
+MAIN    START   BEGIN
+BEGIN   LD      GR1,A
+        CPL     GR1,B
+        RET
+A       DC      #5000
+B       DC      #5000
+        END
+
+Assemble ../../../../as/cmd/CPL/cpl_r_adr__z.casl (0)
+
+Assemble ../../../../as/cmd/CPL/cpl_r_adr__z.casl (1)
+../../../../as/cmd/CPL/cpl_r_adr__z.casl:    1:;;; CPL r,adr ZF:0
+../../../../as/cmd/CPL/cpl_r_adr__z.casl:    2:MAIN    START   BEGIN
+../../../../as/cmd/CPL/cpl_r_adr__z.casl:    3:BEGIN   LD      GR1,A
+	#0000	#1010
+	#0001	#0005
+../../../../as/cmd/CPL/cpl_r_adr__z.casl:    4:        CPL     GR1,B
+	#0002	#4110
+	#0003	#0006
+../../../../as/cmd/CPL/cpl_r_adr__z.casl:    5:        RET
+	#0004	#8100
+../../../../as/cmd/CPL/cpl_r_adr__z.casl:    6:A       DC      #5000
+	#0005	#5000
+../../../../as/cmd/CPL/cpl_r_adr__z.casl:    7:B       DC      #5000
+	#0006	#5000
+../../../../as/cmd/CPL/cpl_r_adr__z.casl:    8:        END
+
+Executing machine codes
+#0000: Register::::
+#0000: GR0:      0 = #0000 = 0000000000000000
+#0000: GR1:      0 = #0000 = 0000000000000000
+#0000: GR2:      0 = #0000 = 0000000000000000
+#0000: GR3:      0 = #0000 = 0000000000000000
+#0000: GR4:      0 = #0000 = 0000000000000000
+#0000: GR5:      0 = #0000 = 0000000000000000
+#0000: GR6:      0 = #0000 = 0000000000000000
+#0000: GR7:      0 = #0000 = 0000000000000000
+#0000: SP:       8 = #0008 = 0000000000001000
+#0000: PR:       0 = #0000 = 0000000000000000
+#0000: FR (OF SF ZF): 000
+#0000: Memory::::
+#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007
+#0000: 0000: 1010 0005 4110 0006 8100 5000 5000 0000 
+#0002: Register::::
+#0002: GR0:      0 = #0000 = 0000000000000000
+#0002: GR1:  20480 = #5000 = 0101000000000000
+#0002: GR2:      0 = #0000 = 0000000000000000
+#0002: GR3:      0 = #0000 = 0000000000000000
+#0002: GR4:      0 = #0000 = 0000000000000000
+#0002: GR5:      0 = #0000 = 0000000000000000
+#0002: GR6:      0 = #0000 = 0000000000000000
+#0002: GR7:      0 = #0000 = 0000000000000000
+#0002: SP:       8 = #0008 = 0000000000001000
+#0002: PR:       2 = #0002 = 0000000000000010
+#0002: FR (OF SF ZF): 000
+#0002: Memory::::
+#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007
+#0002: 0000: 1010 0005 4110 0006 8100 5000 5000 0000 
+#0004: Register::::
+#0004: GR0:      0 = #0000 = 0000000000000000
+#0004: GR1:  20480 = #5000 = 0101000000000000
+#0004: GR2:      0 = #0000 = 0000000000000000
+#0004: GR3:      0 = #0000 = 0000000000000000
+#0004: GR4:      0 = #0000 = 0000000000000000
+#0004: GR5:      0 = #0000 = 0000000000000000
+#0004: GR6:      0 = #0000 = 0000000000000000
+#0004: GR7:      0 = #0000 = 0000000000000000
+#0004: SP:       8 = #0008 = 0000000000001000
+#0004: PR:       4 = #0004 = 0000000000000100
+#0004: FR (OF SF ZF): 001
+#0004: Memory::::
+#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
+#0004: 0000: 1010 0005 4110 0006 8100 5000 5000 0000