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diff --git a/test/system/casl2_cmd/cmd_xor_r1_r2__clear/0.txt b/test/system/casl2_cmd/cmd_xor_r1_r2__clear/0.txt
new file mode 100644
index 0000000..456e7a1
--- /dev/null
+++ b/test/system/casl2_cmd/cmd_xor_r1_r2__clear/0.txt
@@ -0,0 +1,70 @@
+;;; XOR r1,r2 rの内容をクリア
+MAIN    START
+BEGIN   LD      GR1,A
+        XOR     GR1,GR1
+        RET
+A       DC      3
+        END
+
+Assemble ../../../../as/cmd/XOR/xor_r1_r2__clear.casl (0)
+
+Assemble ../../../../as/cmd/XOR/xor_r1_r2__clear.casl (1)
+../../../../as/cmd/XOR/xor_r1_r2__clear.casl:    1:;;; XOR r1,r2 rの内容をクリア
+../../../../as/cmd/XOR/xor_r1_r2__clear.casl:    2:MAIN    START
+../../../../as/cmd/XOR/xor_r1_r2__clear.casl:    3:BEGIN   LD      GR1,A
+	#0000	#1010
+	#0001	#0004
+../../../../as/cmd/XOR/xor_r1_r2__clear.casl:    4:        XOR     GR1,GR1
+	#0002	#3611
+../../../../as/cmd/XOR/xor_r1_r2__clear.casl:    5:        RET
+	#0003	#8100
+../../../../as/cmd/XOR/xor_r1_r2__clear.casl:    6:A       DC      3
+	#0004	#0003
+../../../../as/cmd/XOR/xor_r1_r2__clear.casl:    7:        END
+
+Executing machine codes
+#0000: Register::::
+#0000: GR0:      0 = #0000 = 0000000000000000
+#0000: GR1:      0 = #0000 = 0000000000000000
+#0000: GR2:      0 = #0000 = 0000000000000000
+#0000: GR3:      0 = #0000 = 0000000000000000
+#0000: GR4:      0 = #0000 = 0000000000000000
+#0000: GR5:      0 = #0000 = 0000000000000000
+#0000: GR6:      0 = #0000 = 0000000000000000
+#0000: GR7:      0 = #0000 = 0000000000000000
+#0000: SP:       8 = #0008 = 0000000000001000
+#0000: PR:       0 = #0000 = 0000000000000000
+#0000: FR (OF SF ZF): 000
+#0000: Memory::::
+#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007
+#0000: 0000: 1010 0004 3611 8100 0003 0000 0000 0000 
+#0002: Register::::
+#0002: GR0:      0 = #0000 = 0000000000000000
+#0002: GR1:      3 = #0003 = 0000000000000011
+#0002: GR2:      0 = #0000 = 0000000000000000
+#0002: GR3:      0 = #0000 = 0000000000000000
+#0002: GR4:      0 = #0000 = 0000000000000000
+#0002: GR5:      0 = #0000 = 0000000000000000
+#0002: GR6:      0 = #0000 = 0000000000000000
+#0002: GR7:      0 = #0000 = 0000000000000000
+#0002: SP:       8 = #0008 = 0000000000001000
+#0002: PR:       2 = #0002 = 0000000000000010
+#0002: FR (OF SF ZF): 000
+#0002: Memory::::
+#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007
+#0002: 0000: 1010 0004 3611 8100 0003 0000 0000 0000 
+#0003: Register::::
+#0003: GR0:      0 = #0000 = 0000000000000000
+#0003: GR1:      0 = #0000 = 0000000000000000
+#0003: GR2:      0 = #0000 = 0000000000000000
+#0003: GR3:      0 = #0000 = 0000000000000000
+#0003: GR4:      0 = #0000 = 0000000000000000
+#0003: GR5:      0 = #0000 = 0000000000000000
+#0003: GR6:      0 = #0000 = 0000000000000000
+#0003: GR7:      0 = #0000 = 0000000000000000
+#0003: SP:       8 = #0008 = 0000000000001000
+#0003: PR:       3 = #0003 = 0000000000000011
+#0003: FR (OF SF ZF): 001
+#0003: Memory::::
+#0003: adr : 0000 0001 0002 0003 0004 0005 0006 0007
+#0003: 0000: 1010 0004 3611 8100 0003 0000 0000 0000