test/astest/dc_overflow/0.txt

   1
   2 Assemble ../../../as/dc_overflow.casl (0)
   3 ../../../as/dc_overflow.casl:1:MAIN     START   BEGIN
   4 ../../../as/dc_overflow.casl:2:BEGIN    LD      GR0,A
   5 ../../../as/dc_overflow.casl:3: ADDL    GR0,B
   6 ../../../as/dc_overflow.casl:4: ST      GR0,C
   7 ../../../as/dc_overflow.casl:5: RET
   8 ../../../as/dc_overflow.casl:6:A        DC      32779
   9 ../../../as/dc_overflow.casl:7:B        DC      32778
  10 ../../../as/dc_overflow.casl:8:C        DS      1
  11 ../../../as/dc_overflow.casl:9: END
  12
  13 Label::::
  14 A ---> #0007
  15 B ---> #0008
  16 C ---> #0009
  17 BEGIN ---> #0000
  18 MAIN ---> #0000
  19
  20 Assemble ../../../as/dc_overflow.casl (1)
  21 ../../../as/dc_overflow.casl:1:MAIN     START   BEGIN
  22 ../../../as/dc_overflow.casl:2:BEGIN    LD      GR0,A
  23         #0000   #1000
  24         #0001   #0007
  25 ../../../as/dc_overflow.casl:3: ADDL    GR0,B
  26         #0002   #2200
  27         #0003   #0008
  28 ../../../as/dc_overflow.casl:4: ST      GR0,C
  29         #0004   #1100
  30         #0005   #0009
  31 ../../../as/dc_overflow.casl:5: RET
  32         #0006   #8100
  33 ../../../as/dc_overflow.casl:6:A        DC      32779
  34         #0007   #000B
  35 ../../../as/dc_overflow.casl:7:B        DC      32778
  36         #0008   #000A
  37 ../../../as/dc_overflow.casl:8:C        DS      1
  38         #0009   #0000
  39 ../../../as/dc_overflow.casl:9: END
  40
  41 Executing machine codes
  42 #0000: Register::::
  43 #0000: GR0:      0 = #0000 = 0000000000000000
  44 #0000: GR1:      0 = #0000 = 0000000000000000
  45 #0000: GR2:      0 = #0000 = 0000000000000000
  46 #0000: GR3:      0 = #0000 = 0000000000000000
  47 #0000: GR4:      0 = #0000 = 0000000000000000
  48 #0000: GR5:      0 = #0000 = 0000000000000000
  49 #0000: GR6:      0 = #0000 = 0000000000000000
  50 #0000: GR7:      0 = #0000 = 0000000000000000
  51 #0000: SP:     512 = #0200 = 0000001000000000
  52 #0000: PR:       0 = #0000 = 0000000000000000
  53 #0000: FR (OF SF ZF): 000
  54
  55 #0002: Register::::
  56 #0002: GR0:     11 = #000B = 0000000000001011
  57 #0002: GR1:      0 = #0000 = 0000000000000000
  58 #0002: GR2:      0 = #0000 = 0000000000000000
  59 #0002: GR3:      0 = #0000 = 0000000000000000
  60 #0002: GR4:      0 = #0000 = 0000000000000000
  61 #0002: GR5:      0 = #0000 = 0000000000000000
  62 #0002: GR6:      0 = #0000 = 0000000000000000
  63 #0002: GR7:      0 = #0000 = 0000000000000000
  64 #0002: SP:     512 = #0200 = 0000001000000000
  65 #0002: PR:       2 = #0002 = 0000000000000010
  66 #0002: FR (OF SF ZF): 000
  67
  68 #0004: Register::::
  69 #0004: GR0:     21 = #0015 = 0000000000010101
  70 #0004: GR1:      0 = #0000 = 0000000000000000
  71 #0004: GR2:      0 = #0000 = 0000000000000000
  72 #0004: GR3:      0 = #0000 = 0000000000000000
  73 #0004: GR4:      0 = #0000 = 0000000000000000
  74 #0004: GR5:      0 = #0000 = 0000000000000000
  75 #0004: GR6:      0 = #0000 = 0000000000000000
  76 #0004: GR7:      0 = #0000 = 0000000000000000
  77 #0004: SP:     512 = #0200 = 0000001000000000
  78 #0004: PR:       4 = #0004 = 0000000000000100
  79 #0004: FR (OF SF ZF): 000
  80
  81 #0006: Register::::
  82 #0006: GR0:     21 = #0015 = 0000000000010101
  83 #0006: GR1:      0 = #0000 = 0000000000000000
  84 #0006: GR2:      0 = #0000 = 0000000000000000
  85 #0006: GR3:      0 = #0000 = 0000000000000000
  86 #0006: GR4:      0 = #0000 = 0000000000000000
  87 #0006: GR5:      0 = #0000 = 0000000000000000
  88 #0006: GR6:      0 = #0000 = 0000000000000000
  89 #0006: GR7:      0 = #0000 = 0000000000000000
  90 #0006: SP:     512 = #0200 = 0000001000000000
  91 #0006: PR:       6 = #0006 = 0000000000000110
  92 #0006: FR (OF SF ZF): 000
  93