X-Git-Url: http://j8takagi.net/cgi-bin/gitweb.cgi?p=YACASL2.git;a=blobdiff_plain;f=test%2Fsystem%2Fcasl2_cmd%2Fcmd_cpa_r_adr__ls%2F0.txt;fp=test%2Fsystem%2Fcasl2_cmd%2Fcmd_cpa_r_adr__ls%2F0.txt;h=2165244ad8cf6dfa6c1550e12a70b9f5d7601633;hp=0000000000000000000000000000000000000000;hb=473906d23322ef829ee8dad807895235d645981c;hpb=7ac339dcd755848e9820142422752fbdc8186b5c

diff --git a/test/system/casl2_cmd/cmd_cpa_r_adr__ls/0.txt b/test/system/casl2_cmd/cmd_cpa_r_adr__ls/0.txt
new file mode 100644
index 0000000..2165244
--- /dev/null
+++ b/test/system/casl2_cmd/cmd_cpa_r_adr__ls/0.txt
@@ -0,0 +1,74 @@
+;;; CPA r,adr
+MAIN    START   BEGIN
+BEGIN   LD      GR1,A
+        CPA     GR1,B
+        RET
+A       DC      #5000
+B       DC      #8000
+        END
+
+Assemble ../../../../as/cmd/CPA/cpa_r_adr__ls.casl (0)
+
+Assemble ../../../../as/cmd/CPA/cpa_r_adr__ls.casl (1)
+../../../../as/cmd/CPA/cpa_r_adr__ls.casl:    1:;;; CPA r,adr
+../../../../as/cmd/CPA/cpa_r_adr__ls.casl:    2:MAIN    START   BEGIN
+../../../../as/cmd/CPA/cpa_r_adr__ls.casl:    3:BEGIN   LD      GR1,A
+	#0000	#1010
+	#0001	#0005
+../../../../as/cmd/CPA/cpa_r_adr__ls.casl:    4:        CPA     GR1,B
+	#0002	#4010
+	#0003	#0006
+../../../../as/cmd/CPA/cpa_r_adr__ls.casl:    5:        RET
+	#0004	#8100
+../../../../as/cmd/CPA/cpa_r_adr__ls.casl:    6:A       DC      #5000
+	#0005	#5000
+../../../../as/cmd/CPA/cpa_r_adr__ls.casl:    7:B       DC      #8000
+	#0006	#8000
+../../../../as/cmd/CPA/cpa_r_adr__ls.casl:    8:        END
+
+Executing machine codes
+#0000: Register::::
+#0000: GR0:      0 = #0000 = 0000000000000000
+#0000: GR1:      0 = #0000 = 0000000000000000
+#0000: GR2:      0 = #0000 = 0000000000000000
+#0000: GR3:      0 = #0000 = 0000000000000000
+#0000: GR4:      0 = #0000 = 0000000000000000
+#0000: GR5:      0 = #0000 = 0000000000000000
+#0000: GR6:      0 = #0000 = 0000000000000000
+#0000: GR7:      0 = #0000 = 0000000000000000
+#0000: SP:       8 = #0008 = 0000000000001000
+#0000: PR:       0 = #0000 = 0000000000000000
+#0000: FR (OF SF ZF): 000
+#0000: Memory::::
+#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007
+#0000: 0000: 1010 0005 4010 0006 8100 5000 8000 0000 
+#0002: Register::::
+#0002: GR0:      0 = #0000 = 0000000000000000
+#0002: GR1:  20480 = #5000 = 0101000000000000
+#0002: GR2:      0 = #0000 = 0000000000000000
+#0002: GR3:      0 = #0000 = 0000000000000000
+#0002: GR4:      0 = #0000 = 0000000000000000
+#0002: GR5:      0 = #0000 = 0000000000000000
+#0002: GR6:      0 = #0000 = 0000000000000000
+#0002: GR7:      0 = #0000 = 0000000000000000
+#0002: SP:       8 = #0008 = 0000000000001000
+#0002: PR:       2 = #0002 = 0000000000000010
+#0002: FR (OF SF ZF): 000
+#0002: Memory::::
+#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007
+#0002: 0000: 1010 0005 4010 0006 8100 5000 8000 0000 
+#0004: Register::::
+#0004: GR0:      0 = #0000 = 0000000000000000
+#0004: GR1:  20480 = #5000 = 0101000000000000
+#0004: GR2:      0 = #0000 = 0000000000000000
+#0004: GR3:      0 = #0000 = 0000000000000000
+#0004: GR4:      0 = #0000 = 0000000000000000
+#0004: GR5:      0 = #0000 = 0000000000000000
+#0004: GR6:      0 = #0000 = 0000000000000000
+#0004: GR7:      0 = #0000 = 0000000000000000
+#0004: SP:       8 = #0008 = 0000000000001000
+#0004: PR:       4 = #0004 = 0000000000000100
+#0004: FR (OF SF ZF): 000
+#0004: Memory::::
+#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
+#0004: 0000: 1010 0005 4010 0006 8100 5000 8000 0000