X-Git-Url: http://j8takagi.net/cgi-bin/gitweb.cgi?p=YACASL2.git;a=blobdiff_plain;f=test%2Fsystem%2Fcasl2_cmd%2Fcmd_jze__o%2F0.txt;fp=test%2Fsystem%2Fcasl2_cmd%2Fcmd_jze__o%2F0.txt;h=6d00c9fc6d6f967f1cd2ee2fb58603c78a9d5d0b;hp=0000000000000000000000000000000000000000;hb=473906d23322ef829ee8dad807895235d645981c;hpb=7ac339dcd755848e9820142422752fbdc8186b5c diff --git a/test/system/casl2_cmd/cmd_jze__o/0.txt b/test/system/casl2_cmd/cmd_jze__o/0.txt new file mode 100644 index 0000000..6d00c9f --- /dev/null +++ b/test/system/casl2_cmd/cmd_jze__o/0.txt @@ -0,0 +1,138 @@ +;;; JZE adr OF:1/SF:0/ZF:0 +MAIN START + LD GR1,A + SRL GR1,1 + JZE TO + LAD GR1,0 + JUMP FIN +TO LAD GR1,#FFFF +FIN RET +A DC #0003 + END + +Assemble ../../../../as/cmd/JZE/jze__o.casl (0) + +Assemble ../../../../as/cmd/JZE/jze__o.casl (1) +../../../../as/cmd/JZE/jze__o.casl: 1:;;; JZE adr OF:1/SF:0/ZF:0 +../../../../as/cmd/JZE/jze__o.casl: 2:MAIN START +../../../../as/cmd/JZE/jze__o.casl: 3: LD GR1,A + #0000 #1010 + #0001 #000D +../../../../as/cmd/JZE/jze__o.casl: 4: SRL GR1,1 + #0002 #5310 + #0003 #0001 +../../../../as/cmd/JZE/jze__o.casl: 5: JZE TO + #0004 #6300 + #0005 #000A +../../../../as/cmd/JZE/jze__o.casl: 6: LAD GR1,0 + #0006 #1210 + #0007 #0000 +../../../../as/cmd/JZE/jze__o.casl: 7: JUMP FIN + #0008 #6400 + #0009 #000C +../../../../as/cmd/JZE/jze__o.casl: 8:TO LAD GR1,#FFFF + #000A #1210 + #000B #FFFF +../../../../as/cmd/JZE/jze__o.casl: 9:FIN RET + #000C #8100 +../../../../as/cmd/JZE/jze__o.casl: 10:A DC #0003 + #000D #0003 +../../../../as/cmd/JZE/jze__o.casl: 11: END + +Executing machine codes +#0000: Register:::: +#0000: GR0: 0 = #0000 = 0000000000000000 +#0000: GR1: 0 = #0000 = 0000000000000000 +#0000: GR2: 0 = #0000 = 0000000000000000 +#0000: GR3: 0 = #0000 = 0000000000000000 +#0000: GR4: 0 = #0000 = 0000000000000000 +#0000: GR5: 0 = #0000 = 0000000000000000 +#0000: GR6: 0 = #0000 = 0000000000000000 +#0000: GR7: 0 = #0000 = 0000000000000000 +#0000: SP: 16 = #0010 = 0000000000010000 +#0000: PR: 0 = #0000 = 0000000000000000 +#0000: FR (OF SF ZF): 000 +#0000: Memory:::: +#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F +#0000: 0000: 1010 000D 5310 0001 6300 000A 1210 0000 6400 000C 1210 FFFF 8100 0003 0000 0000 + +#0002: Register:::: +#0002: GR0: 0 = #0000 = 0000000000000000 +#0002: GR1: 3 = #0003 = 0000000000000011 +#0002: GR2: 0 = #0000 = 0000000000000000 +#0002: GR3: 0 = #0000 = 0000000000000000 +#0002: GR4: 0 = #0000 = 0000000000000000 +#0002: GR5: 0 = #0000 = 0000000000000000 +#0002: GR6: 0 = #0000 = 0000000000000000 +#0002: GR7: 0 = #0000 = 0000000000000000 +#0002: SP: 16 = #0010 = 0000000000010000 +#0002: PR: 2 = #0002 = 0000000000000010 +#0002: FR (OF SF ZF): 000 +#0002: Memory:::: +#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F +#0002: 0000: 1010 000D 5310 0001 6300 000A 1210 0000 6400 000C 1210 FFFF 8100 0003 0000 0000 + +#0004: Register:::: +#0004: GR0: 0 = #0000 = 0000000000000000 +#0004: GR1: 1 = #0001 = 0000000000000001 +#0004: GR2: 0 = #0000 = 0000000000000000 +#0004: GR3: 0 = #0000 = 0000000000000000 +#0004: GR4: 0 = #0000 = 0000000000000000 +#0004: GR5: 0 = #0000 = 0000000000000000 +#0004: GR6: 0 = #0000 = 0000000000000000 +#0004: GR7: 0 = #0000 = 0000000000000000 +#0004: SP: 16 = #0010 = 0000000000010000 +#0004: PR: 4 = #0004 = 0000000000000100 +#0004: FR (OF SF ZF): 100 +#0004: Memory:::: +#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F +#0004: 0000: 1010 000D 5310 0001 6300 000A 1210 0000 6400 000C 1210 FFFF 8100 0003 0000 0000 + +#0006: Register:::: +#0006: GR0: 0 = #0000 = 0000000000000000 +#0006: GR1: 1 = #0001 = 0000000000000001 +#0006: GR2: 0 = #0000 = 0000000000000000 +#0006: GR3: 0 = #0000 = 0000000000000000 +#0006: GR4: 0 = #0000 = 0000000000000000 +#0006: GR5: 0 = #0000 = 0000000000000000 +#0006: GR6: 0 = #0000 = 0000000000000000 +#0006: GR7: 0 = #0000 = 0000000000000000 +#0006: SP: 16 = #0010 = 0000000000010000 +#0006: PR: 6 = #0006 = 0000000000000110 +#0006: FR (OF SF ZF): 100 +#0006: Memory:::: +#0006: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F +#0006: 0000: 1010 000D 5310 0001 6300 000A 1210 0000 6400 000C 1210 FFFF 8100 0003 0000 0000 + +#0008: Register:::: +#0008: GR0: 0 = #0000 = 0000000000000000 +#0008: GR1: 0 = #0000 = 0000000000000000 +#0008: GR2: 0 = #0000 = 0000000000000000 +#0008: GR3: 0 = #0000 = 0000000000000000 +#0008: GR4: 0 = #0000 = 0000000000000000 +#0008: GR5: 0 = #0000 = 0000000000000000 +#0008: GR6: 0 = #0000 = 0000000000000000 +#0008: GR7: 0 = #0000 = 0000000000000000 +#0008: SP: 16 = #0010 = 0000000000010000 +#0008: PR: 8 = #0008 = 0000000000001000 +#0008: FR (OF SF ZF): 100 +#0008: Memory:::: +#0008: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F +#0008: 0000: 1010 000D 5310 0001 6300 000A 1210 0000 6400 000C 1210 FFFF 8100 0003 0000 0000 + +#000C: Register:::: +#000C: GR0: 0 = #0000 = 0000000000000000 +#000C: GR1: 0 = #0000 = 0000000000000000 +#000C: GR2: 0 = #0000 = 0000000000000000 +#000C: GR3: 0 = #0000 = 0000000000000000 +#000C: GR4: 0 = #0000 = 0000000000000000 +#000C: GR5: 0 = #0000 = 0000000000000000 +#000C: GR6: 0 = #0000 = 0000000000000000 +#000C: GR7: 0 = #0000 = 0000000000000000 +#000C: SP: 16 = #0010 = 0000000000010000 +#000C: PR: 12 = #000C = 0000000000001100 +#000C: FR (OF SF ZF): 100 +#000C: Memory:::: +#000C: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F +#000C: 0000: 1010 000D 5310 0001 6300 000A 1210 0000 6400 000C 1210 FFFF 8100 0003 0000 0000 +