SUBL GR1,B
RET
A DC #7FFE ; 32766
-B DC #FFF6 ; -10
+B DC #FFF6 ; 65526
END
LD GR1,A
SUBL GR1,B
RET
-A DC #FFEC ; -20
-B DC #FFF6 ; -10
+A DC #FFEC ; 65516
+B DC #FFF6 ; 65526
END
LD GR1,A
SUBL GR1,B
RET
-A DC #FFF6 ; -10
-B DC #FFF6 ; -10
+A DC #FFF6 ; 65526
+B DC #FFF6 ; 65526
END
MAIN START
LAD GR1,0
- LAD GR2,15
+ LAD GR2,17
LAD GR3,OP
CALL DIV
RET
sys->cpu->pr += 1;
}
-void addl_subl_flagset(long val)
-{
- sys->cpu->fr = 0x0;
-
- if(val > 65535) {
- sys->cpu->fr += OF;
- }
- if(((WORD)(val) & 0x8000) == 0x8000) {
- sys->cpu->fr += SF;
- } else if(val == 0x0) {
- sys->cpu->fr += ZF;
- }
-}
-
-void addl(WORD r, WORD val)
-{
- long s;
-
- s = sys->cpu->gr[r] + val;
- sys->cpu->gr[r] = (WORD)s;
- addl_subl_flagset(s);
-}
-
-void subl(WORD r, WORD val)
+void addl_gr(WORD r, WORD val, bool add)
{
unsigned long o, s;
o = sys->cpu->gr[r];
- if((s = o + (~val + 1)) > 0x10000) {
- s -= 0x10000;
+ sys->cpu->fr = 0x0; /* flag initialize */
+
+ if(add == true) {
+ s = o + val;
+ if(s > 0xFFFF) {
+ sys->cpu->fr += OF;
+ }
+ } else {
+ if(o < val) {
+ sys->cpu->fr += OF;
+ }
+ s = o + (~val + 1);
+ if(s > 0xFFFF) {
+ s &= 0xFFFF;
+ }
}
sys->cpu->gr[r] = (WORD)s;
- addl_subl_flagset(s);
- if(o < val) {
- sys->cpu->fr += OF;
+
+ if((s & 0x8000) == 0x8000) {
+ sys->cpu->fr += SF;
+ }
+ else if(s == 0x0) {
+ sys->cpu->fr += ZF;
}
}
WORD w[2];
w[0] = sys->memory[sys->cpu->pr];
w[1] = sys->memory[sys->cpu->pr + 1];
- addl(get_r_r1(w[0]), get_val_adr_x(w[1], w[0]));
+ addl_gr(get_r_r1(w[0]), get_val_adr_x(w[1], w[0]), true);
sys->cpu->pr += 2;
}
{
WORD w[1];
w[0] = sys->memory[sys->cpu->pr];
- addl(get_r_r1(w[0]), sys->cpu->gr[get_x_r2(w[0])]);
+ addl_gr(get_r_r1(w[0]), sys->cpu->gr[get_x_r2(w[0])], true);
sys->cpu->pr += 1;
}
WORD w[2];
w[0] = sys->memory[sys->cpu->pr];
w[1] = sys->memory[sys->cpu->pr + 1];
- subl(get_r_r1(w[0]), (get_val_adr_x(w[1], w[0])));
+ addl_gr(get_r_r1(w[0]), get_val_adr_x(w[1], w[0]), false);
sys->cpu->pr += 2;
}
{
WORD w[1];
w[0] = sys->memory[sys->cpu->pr];
- subl(get_r_r1(w[0]), (sys->cpu->gr[get_x_r2(w[0])]));
+ addl_gr(get_r_r1(w[0]), sys->cpu->gr[get_x_r2(w[0])], false);
sys->cpu->pr += 1;
}
cat ../../../../as/cmd/ADDL/addl_r1_r2.casl
-../../../../casl2 -atd -M16 ../../../../as/cmd/ADDL/addl_r1_r2.casl
+../../../../casl2 -aTd -M16 ../../../../as/cmd/ADDL/addl_r1_r2.casl
cat ../../../../as/cmd/ADDL/addl_r_adr.casl
-../../../../casl2 -atd -M8 ../../../../as/cmd/ADDL/addl_r_adr.casl
+../../../../casl2 -aTd -M8 ../../../../as/cmd/ADDL/addl_r_adr.casl
#0002: 0000: 1010 0005 2210 0006 8100 000A FFEC 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: -10 = #FFF6 = 1111111111110110
+#0004: GR1: 65526 = #FFF6 = 1111111111110110
#0004: GR2: 0 = #0000 = 0000000000000000
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
cat ../../../../as/cmd/ADDL/addl_r_adr__as0.casl
-../../../../casl2 -atd -M8 ../../../../as/cmd/ADDL/addl_r_adr__as0.casl
+../../../../casl2 -aTd -M8 ../../../../as/cmd/ADDL/addl_r_adr__as0.casl
+++ /dev/null
-;;; ADDL r,adr,x
-MAIN START
-BEGIN LD GR1,A
- LAD GR2,1
- ADDL GR1,A,GR2
- RET
-A DC 3
- DC 1
- END
-
-Assemble ../../../../as/cmd/ADDL/addl1.casl (0)
-
-Assemble ../../../../as/cmd/ADDL/addl1.casl (1)
-../../../../as/cmd/ADDL/addl1.casl: 1:;;; ADDL r,adr,x
-../../../../as/cmd/ADDL/addl1.casl: 2:MAIN START
-../../../../as/cmd/ADDL/addl1.casl: 3:BEGIN LD GR1,A
- #0000 #1010
- #0001 #0007
-../../../../as/cmd/ADDL/addl1.casl: 4: LAD GR2,1
- #0002 #1220
- #0003 #0001
-../../../../as/cmd/ADDL/addl1.casl: 5: ADDL GR1,A,GR2
- #0004 #2212
- #0005 #0007
-../../../../as/cmd/ADDL/addl1.casl: 6: RET
- #0006 #8100
-../../../../as/cmd/ADDL/addl1.casl: 7:A DC 3
- #0007 #0003
-../../../../as/cmd/ADDL/addl1.casl: 8: DC 1
- #0008 #0001
-../../../../as/cmd/ADDL/addl1.casl: 9: END
-
-Executing machine codes
-#0000: Register::::
-#0000: GR0: 0 = #0000 = 0000000000000000
-#0000: GR1: 0 = #0000 = 0000000000000000
-#0000: GR2: 0 = #0000 = 0000000000000000
-#0000: GR3: 0 = #0000 = 0000000000000000
-#0000: GR4: 0 = #0000 = 0000000000000000
-#0000: GR5: 0 = #0000 = 0000000000000000
-#0000: GR6: 0 = #0000 = 0000000000000000
-#0000: GR7: 0 = #0000 = 0000000000000000
-#0000: SP: 16 = #0010 = 0000000000010000
-#0000: PR: 0 = #0000 = 0000000000000000
-#0000: FR (OF SF ZF): 000
-#0000: Memory::::
-#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0000: 0000: 1010 0007 1220 0001 2212 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
-
-#0002: Register::::
-#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: 3 = #0003 = 0000000000000011
-#0002: GR2: 0 = #0000 = 0000000000000000
-#0002: GR3: 0 = #0000 = 0000000000000000
-#0002: GR4: 0 = #0000 = 0000000000000000
-#0002: GR5: 0 = #0000 = 0000000000000000
-#0002: GR6: 0 = #0000 = 0000000000000000
-#0002: GR7: 0 = #0000 = 0000000000000000
-#0002: SP: 16 = #0010 = 0000000000010000
-#0002: PR: 2 = #0002 = 0000000000000010
-#0002: FR (OF SF ZF): 000
-#0002: Memory::::
-#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0002: 0000: 1010 0007 1220 0001 2212 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
-
-#0004: Register::::
-#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: 3 = #0003 = 0000000000000011
-#0004: GR2: 1 = #0001 = 0000000000000001
-#0004: GR3: 0 = #0000 = 0000000000000000
-#0004: GR4: 0 = #0000 = 0000000000000000
-#0004: GR5: 0 = #0000 = 0000000000000000
-#0004: GR6: 0 = #0000 = 0000000000000000
-#0004: GR7: 0 = #0000 = 0000000000000000
-#0004: SP: 16 = #0010 = 0000000000010000
-#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 000
-#0004: Memory::::
-#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0004: 0000: 1010 0007 1220 0001 2212 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
-
-#0006: Register::::
-#0006: GR0: 0 = #0000 = 0000000000000000
-#0006: GR1: 4 = #0004 = 0000000000000100
-#0006: GR2: 1 = #0001 = 0000000000000001
-#0006: GR3: 0 = #0000 = 0000000000000000
-#0006: GR4: 0 = #0000 = 0000000000000000
-#0006: GR5: 0 = #0000 = 0000000000000000
-#0006: GR6: 0 = #0000 = 0000000000000000
-#0006: GR7: 0 = #0000 = 0000000000000000
-#0006: SP: 16 = #0010 = 0000000000010000
-#0006: PR: 6 = #0006 = 0000000000000110
-#0006: FR (OF SF ZF): 000
-#0006: Memory::::
-#0006: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0006: 0000: 1010 0007 1220 0001 2212 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
-
+++ /dev/null
-include ../Define.mk
-include ../Test.mk
+++ /dev/null
-cat ../../../../as/cmd/ADDL/addl1.casl
-../../../../casl2 -atd -M16 ../../../../as/cmd/ADDL/addl1.casl
cat ../../../../as/cmd/SUBL/subl_r1_r2.casl
-../../../../casl2 -atd -M16 ../../../../as/cmd/SUBL/subl_r1_r2.casl
+../../../../casl2 -aTd -M16 ../../../../as/cmd/SUBL/subl_r1_r2.casl
cat ../../../../as/cmd/SUBL/subl_r_adr.casl
-../../../../casl2 -atd -M8 ../../../../as/cmd/SUBL/subl_r_adr.casl
+../../../../casl2 -aTd -M8 ../../../../as/cmd/SUBL/subl_r_adr.casl
SUBL GR1,B
RET
A DC #7FFE ; 32766
-B DC #FFF6 ; -10
+B DC #FFF6 ; 65526
END
Assemble ../../../../as/cmd/SUBL/subl_r_adr__ao.casl (0)
#0004 #8100
../../../../as/cmd/SUBL/subl_r_adr__ao.casl: 6:A DC #7FFE ; 32766
#0005 #7FFE
-../../../../as/cmd/SUBL/subl_r_adr__ao.casl: 7:B DC #FFF6 ; -10
+../../../../as/cmd/SUBL/subl_r_adr__ao.casl: 7:B DC #FFF6 ; 65526
#0006 #FFF6
../../../../as/cmd/SUBL/subl_r_adr__ao.casl: 8: END
#0002: 0000: 1010 0005 2310 0006 8100 000A 0014 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: -10 = #FFF6 = 1111111111110110
+#0004: GR1: 65526 = #FFF6 = 1111111111110110
#0004: GR2: 0 = #0000 = 0000000000000000
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
cat ../../../../as/cmd/SUBL/subl_r_adr__as0.casl
-../../../../casl2 -atd -M8 ../../../../as/cmd/SUBL/subl_r_adr__as0.casl
+../../../../casl2 -aTd -M8 ../../../../as/cmd/SUBL/subl_r_adr__as0.casl
LD GR1,A
SUBL GR1,B
RET
-A DC #FFEC ; -20
-B DC #FFF6 ; -10
+A DC #FFEC ; 65516
+B DC #FFF6 ; 65526
END
Assemble ../../../../as/cmd/SUBL/subl_r_adr__as1.casl (0)
#0003 #0006
../../../../as/cmd/SUBL/subl_r_adr__as1.casl: 5: RET
#0004 #8100
-../../../../as/cmd/SUBL/subl_r_adr__as1.casl: 6:A DC #FFEC ; -20
+../../../../as/cmd/SUBL/subl_r_adr__as1.casl: 6:A DC #FFEC ; 65516
#0005 #FFEC
-../../../../as/cmd/SUBL/subl_r_adr__as1.casl: 7:B DC #FFF6 ; -10
+../../../../as/cmd/SUBL/subl_r_adr__as1.casl: 7:B DC #FFF6 ; 65526
#0006 #FFF6
../../../../as/cmd/SUBL/subl_r_adr__as1.casl: 8: END
LD GR1,A
SUBL GR1,B
RET
-A DC #FFF6 ; -10
-B DC #FFF6 ; -10
+A DC #FFF6 ; 65526
+B DC #FFF6 ; 65526
END
Assemble ../../../../as/cmd/SUBL/subl_r_adr__z.casl (0)
#0003 #0006
../../../../as/cmd/SUBL/subl_r_adr__z.casl: 5: RET
#0004 #8100
-../../../../as/cmd/SUBL/subl_r_adr__z.casl: 6:A DC #FFF6 ; -10
+../../../../as/cmd/SUBL/subl_r_adr__z.casl: 6:A DC #FFF6 ; 65526
#0005 #FFF6
-../../../../as/cmd/SUBL/subl_r_adr__z.casl: 7:B DC #FFF6 ; -10
+../../../../as/cmd/SUBL/subl_r_adr__z.casl: 7:B DC #FFF6 ; 65526
#0006 #FFF6
../../../../as/cmd/SUBL/subl_r_adr__z.casl: 8: END
cat ../../../../as/cmd/SUBL/subl_r_adr_x.casl
-../../../../casl2 -atd -M16 ../../../../as/cmd/SUBL/subl_r_adr_x.casl
+../../../../casl2 -aTd -M16 ../../../../as/cmd/SUBL/subl_r_adr_x.casl
../../../../casl2 -O ../../../../as/cmd/ADDL/addl_r1_r2.casl
-../../../../comet2 -td -M16 a.o
+../../../../comet2 -Td -M16 a.o
rm -f a.o
../../../../casl2 -O ../../../../as/cmd/ADDL/addl_r_adr.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0002: 0000: 1010 0005 2210 0006 8100 7FFE 000A 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: -32760 = #8008 = 1000000000001000
+#0004: GR1: 32776 = #8008 = 1000000000001000
#0004: GR2: 0 = #0000 = 0000000000000000
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
../../../../casl2 -O ../../../../as/cmd/ADDL/addl_r_adr__ao.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0002: 0000: 1010 0005 2210 0006 8100 000A FFEC 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: -10 = #FFF6 = 1111111111110110
+#0004: GR1: 65526 = #FFF6 = 1111111111110110
#0004: GR2: 0 = #0000 = 0000000000000000
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
../../../../casl2 -O ../../../../as/cmd/ADDL/addl_r_adr__as0.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0000: 0000: 1010 0005 2210 0006 8100 FFEC 000A 0000
#0002: Register::::
#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: -20 = #FFEC = 1111111111101100
+#0002: GR1: 65516 = #FFEC = 1111111111101100
#0002: GR2: 0 = #0000 = 0000000000000000
#0002: GR3: 0 = #0000 = 0000000000000000
#0002: GR4: 0 = #0000 = 0000000000000000
#0002: 0000: 1010 0005 2210 0006 8100 FFEC 000A 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: -10 = #FFF6 = 1111111111110110
+#0004: GR1: 65526 = #FFF6 = 1111111111110110
#0004: GR2: 0 = #0000 = 0000000000000000
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
../../../../casl2 -O ../../../../as/cmd/ADDL/addl_r_adr__as1.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0000: 0000: 1010 0005 2210 0006 8100 FFF6 000A 0000
#0002: Register::::
#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: -10 = #FFF6 = 1111111111110110
+#0002: GR1: 65526 = #FFF6 = 1111111111110110
#0002: GR2: 0 = #0000 = 0000000000000000
#0002: GR3: 0 = #0000 = 0000000000000000
#0002: GR4: 0 = #0000 = 0000000000000000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 101
+#0004: FR (OF SF ZF): 100
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2210 0006 8100 FFF6 000A 0000
../../../../casl2 -O ../../../../as/cmd/ADDL/addl_r_adr__az.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0000: 0000: 1010 0005 2210 0006 8100 FFFE 000F 0000
#0002: Register::::
#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: -2 = #FFFE = 1111111111111110
+#0002: GR1: 65534 = #FFFE = 1111111111111110
#0002: GR2: 0 = #0000 = 0000000000000000
#0002: GR3: 0 = #0000 = 0000000000000000
#0002: GR4: 0 = #0000 = 0000000000000000
../../../../casl2 -O ../../../../as/cmd/ADDL/addl_r_adr__lo.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0000: 0000: 1010 0005 2210 0006 8100 8002 8001 0000
#0002: Register::::
#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: -32766 = #8002 = 1000000000000010
+#0002: GR1: 32770 = #8002 = 1000000000000010
#0002: GR2: 0 = #0000 = 0000000000000000
#0002: GR3: 0 = #0000 = 0000000000000000
#0002: GR4: 0 = #0000 = 0000000000000000
../../../../casl2 -O ../../../../as/cmd/ADDL/addl_r_adr__o.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
../../../../casl2 -O ../../../../as/cmd/ADDL/addl_r_adr__z.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
../../../../casl2 -O ../../../../as/cmd/ADDL/addl_r_adr_x.casl
-../../../../comet2 -td -M16 a.o
+../../../../comet2 -Td -M16 a.o
rm -f a.o
#0005: GR7: 0 = #0000 = 0000000000000000
#0005: SP: 16 = #0010 = 0000000000010000
#0005: PR: 5 = #0005 = 0000000000000101
-#0005: FR (OF SF ZF): 100
+#0005: FR (OF SF ZF): 000
#0005: Memory::::
#0005: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
#0005: 0000: 1010 0006 1020 0007 2712 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000 0000
../../../../casl2 -O ../../../../as/cmd/SUBL/subl_r1_r2.casl
-../../../../comet2 -td -M16 a.o
+../../../../comet2 -Td -M16 a.o
rm -f a.o
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 100
+#0004: FR (OF SF ZF): 000
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 0003 0001 0000
../../../../casl2 -O ../../../../as/cmd/SUBL/subl_r_adr.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0002: 0000: 1010 0005 2310 0006 8100 7FFE FFF6 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: -32760 = #8008 = 1000000000001000
+#0004: GR1: 32776 = #8008 = 1000000000001000
#0004: GR2: 0 = #0000 = 0000000000000000
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 010
+#0004: FR (OF SF ZF): 110
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 7FFE FFF6 0000
../../../../casl2 -O ../../../../as/cmd/SUBL/subl_r_adr__ao.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0002: 0000: 1010 0005 2310 0006 8100 000A 0014 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: -10 = #FFF6 = 1111111111110110
+#0004: GR1: 65526 = #FFF6 = 1111111111110110
#0004: GR2: 0 = #0000 = 0000000000000000
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 010
+#0004: FR (OF SF ZF): 110
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 000A 0014 0000
../../../../casl2 -O ../../../../as/cmd/SUBL/subl_r_adr__as0.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0000: 0000: 1010 0005 2310 0006 8100 FFEC FFF6 0000
#0002: Register::::
#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: -20 = #FFEC = 1111111111101100
+#0002: GR1: 65516 = #FFEC = 1111111111101100
#0002: GR2: 0 = #0000 = 0000000000000000
#0002: GR3: 0 = #0000 = 0000000000000000
#0002: GR4: 0 = #0000 = 0000000000000000
#0002: 0000: 1010 0005 2310 0006 8100 FFEC FFF6 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: -10 = #FFF6 = 1111111111110110
+#0004: GR1: 65526 = #FFF6 = 1111111111110110
#0004: GR2: 0 = #0000 = 0000000000000000
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 010
+#0004: FR (OF SF ZF): 110
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 FFEC FFF6 0000
../../../../casl2 -O ../../../../as/cmd/SUBL/subl_r_adr__as1.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0002: 0000: 1010 0005 2310 0006 8100 0002 000F 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: -13 = #FFF3 = 1111111111110011
+#0004: GR1: 65523 = #FFF3 = 1111111111110011
#0004: GR2: 0 = #0000 = 0000000000000000
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 010
+#0004: FR (OF SF ZF): 110
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 0002 000F 0000
../../../../casl2 -O ../../../../as/cmd/SUBL/subl_r_adr__lo.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0000: 0000: 1010 0005 2310 0006 8100 8002 7FFF 0000
#0002: Register::::
#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: -32766 = #8002 = 1000000000000010
+#0002: GR1: 32770 = #8002 = 1000000000000010
#0002: GR2: 0 = #0000 = 0000000000000000
#0002: GR3: 0 = #0000 = 0000000000000000
#0002: GR4: 0 = #0000 = 0000000000000000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 100
+#0004: FR (OF SF ZF): 000
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 8002 7FFF 0000
../../../../casl2 -O ../../../../as/cmd/SUBL/subl_r_adr__o.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0000: 0000: 1010 0005 2310 0006 8100 FFF6 FFF6 0000
#0002: Register::::
#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: -10 = #FFF6 = 1111111111110110
+#0002: GR1: 65526 = #FFF6 = 1111111111110110
#0002: GR2: 0 = #0000 = 0000000000000000
#0002: GR3: 0 = #0000 = 0000000000000000
#0002: GR4: 0 = #0000 = 0000000000000000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 101
+#0004: FR (OF SF ZF): 001
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 FFF6 FFF6 0000
../../../../casl2 -O ../../../../as/cmd/SUBL/subl_r_adr__z.casl
-../../../../comet2 -td -M8 a.o
+../../../../comet2 -Td -M8 a.o
rm -f a.o
#0000: FR (OF SF ZF): 000
#0000: Memory::::
#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0000: 0000: 1010 0007 1220 0001 2312 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
+#0000: 0000: 1010 0007 1220 0001 2312 0007 8100 0005 0002 0000 0000 0000 0000 0000 0000 0000
#0002: Register::::
#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: 3 = #0003 = 0000000000000011
+#0002: GR1: 5 = #0005 = 0000000000000101
#0002: GR2: 0 = #0000 = 0000000000000000
#0002: GR3: 0 = #0000 = 0000000000000000
#0002: GR4: 0 = #0000 = 0000000000000000
#0002: FR (OF SF ZF): 000
#0002: Memory::::
#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0002: 0000: 1010 0007 1220 0001 2312 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
+#0002: 0000: 1010 0007 1220 0001 2312 0007 8100 0005 0002 0000 0000 0000 0000 0000 0000 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: 3 = #0003 = 0000000000000011
+#0004: GR1: 5 = #0005 = 0000000000000101
#0004: GR2: 1 = #0001 = 0000000000000001
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
#0004: FR (OF SF ZF): 000
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0004: 0000: 1010 0007 1220 0001 2312 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
+#0004: 0000: 1010 0007 1220 0001 2312 0007 8100 0005 0002 0000 0000 0000 0000 0000 0000 0000
#0006: Register::::
#0006: GR0: 0 = #0000 = 0000000000000000
-#0006: GR1: 2 = #0002 = 0000000000000010
+#0006: GR1: 3 = #0003 = 0000000000000011
#0006: GR2: 1 = #0001 = 0000000000000001
#0006: GR3: 0 = #0000 = 0000000000000000
#0006: GR4: 0 = #0000 = 0000000000000000
#0006: GR7: 0 = #0000 = 0000000000000000
#0006: SP: 16 = #0010 = 0000000000010000
#0006: PR: 6 = #0006 = 0000000000000110
-#0006: FR (OF SF ZF): 100
+#0006: FR (OF SF ZF): 000
#0006: Memory::::
#0006: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0006: 0000: 1010 0007 1220 0001 2312 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
+#0006: 0000: 1010 0007 1220 0001 2312 0007 8100 0005 0002 0000 0000 0000 0000 0000 0000 0000
../../../../casl2 -O ../../../../as/cmd/SUBL/subl_r_adr_x.casl
-../../../../comet2 -td -M16 a.o
+../../../../comet2 -Td -M16 a.o
rm -f a.o