OUTL START
RPUSH
LAD GR2,10 ; GR2に10進数の「10」を格納。
- LAD GR0,0 ; GR0 <- 0
+ XOR GR0,GR0 ; GR0 <- 0
XOR GR4,GR4 ; 整数値の長さ
AND GR1,GR1 ; GR1をテスト
JZE ZERO ; GR1が0の場合、ZEROにジャンプ
-;;; ADDL r,adr 演算結果が負数(r < adr)
+;;; ADDL r,adr
MAIN START
LD GR1,A
ADDL GR1,B
LD GR1,A
ADDL GR1,B
RET
-A DC #FFF6 ; -10
+A DC #FFF6 ; 65526
B DC 10
END
-;;; SUBL r,adr オーバーフロー
+;;; SUBL r,adr 論理演算ではオーバーフローなし(算術減算ではオーバーフロー)
MAIN START
LD GR1,A
SUBL GR1,B
RET
-A DC #8002 ; -32766
+A DC #8002 ; 32770
B DC #7FFF ; 32767
END
LAD GR2,1
SUBL GR1,A,GR2
RET
-A DC 3
- DC 1
+A DC 5
+ DC 2
END
+https://www.jitec.ipa.go.jp/1_04hanni_sukiru/mondai_kaitou_2011h23_2/2011h23a_fe_pm_qs.pdf P.56 - P.59
次のアセンブラプログラムの説明及びプログラムを読んで,設問1,2に答えよ。
〔プログラム1の説明〕
(2) 副プログラム DIV から戻るとき,汎用レジスタ GR6, GR7 の内容は元に戻す。
+設問1.
プログラム1中の に入れる正しい答えを,解答群の中から選べ。
a に関する解答群
ア JMI ADJ2 イ JMI CONT ウ JOV ADJ2
エ JOV CONT オ JPL ADJ2 カ JPL CONT
+
+設問2.
+10進表記で 0~99999 の値の整数を32ビット符号なし整数として与えたとき,DIV を用いて10進数文字列に変換する副プログラム BTOD を異なるアルゴリズムで2種類作成した。プログラム2は10進表記の上位桁から求めるものであり,プログラム3は10進表記の下位桁から求めるものである。プログラム2,プログラム3中の に入れる正しい答えを,解答群の中から選べ。
+BTOD は32ビット符号なし整数の上位語を GR1 に,下位語を GR2 に,変換結果を格納する領域の先頭アドレスを GR3 に設定して呼び出される。
+変換後の10進数文字列は5語の領域に格納される。ただし,5桁に満たない場合は上位桁に"0"が補われる。対象数値が16進表記で 0000054D の場合の実行結果を,次に示す。
+pm12_3.gif/image-size:317×50
+副プログラム BTOD から戻るとき,汎用レジスタ GR1~GR7 の内容は元に戻す。
LAD GR6,1,GR6
LD GR1,GR4 ; 被除数の再設定
LD GR2,GR5
-
+
JUMP LP
FIN RPOP
RET
-MAIN START
- RPUSH
-
+MAIN START
+ LAD GR1,0
+ LAD GR2,15
+ LAD GR3,OP
+ CALL DIV
+ RET
+OP DC 0,3
+ END
--- /dev/null
+MAIN START
+ LAD GR1,#0000 ; #0000: #1210 #0000
+ LAD GR2,#000F ; #0002: #1220 #000F
+ LAD GR3,#0009 ; #0004: #1230 #0009
+ CALL #000B ; #0006: #8000 #000B
+ RET ; #0008: #8100
+ NOP ; #0009: #0000
+ DC 3 ; #000A: #0003 :: 3 = #0003 = 0000000000000011
+ PUSH #0000,GR6 ; #000B: #7006 #0000
+ PUSH #0000,GR7 ; #000D: #7007 #0000
+ LD GR6,GR1 ; #000F: #1461
+ LD GR7,GR2 ; #0010: #1472
+ LD GR1,#0032 ; #0011: #1010 #0032
+ LD GR2,#0033 ; #0013: #1020 #0033
+ LD GR4,GR6 ; #0015: #1446
+ LD GR5,GR7 ; #0016: #1457
+ ADDL GR2,#0034 ; #0017: #2220 #0034
+ JOV #001D ; #0019: #6600 #001D
+ JUMP #001F ; #001B: #6400 #001F
+ ADDL GR1,#0035 ; #001D: #2210 #0035
+ SUBL GR6,#0000,GR3 ; #001F: #2363 #0000
+ JOV #002F ; #0021: #6600 #002F
+ SUBL GR7,#0001,GR3 ; #0023: #2373 #0001
+ JOV #0029 ; #0025: #6600 #0029
+ JUMP #0015 ; #0027: #6400 #0015
+ SUBL GR6,#0036 ; #0029: #2360 #0036
+ JOV #002F ; #002B: #6600 #002F
+ JUMP #0015 ; #002D: #6400 #0015
+ POP GR7 ; #002F: #7170
+ POP GR6 ; #0030: #7160
+ RET ; #0031: #8100
+ DC 65535 ; #0032: #FFFF :: 65535 = #FFFF = 1111111111111111
+ DC 65535 ; #0033: #FFFF :: 65535 = #FFFF = 1111111111111111
+ DC 1 ; #0034: #0001 :: 1 = #0001 = 0000000000000001
+ DC 1 ; #0035: #0001 :: 1 = #0001 = 0000000000000001
+ DC 1 ; #0036: #0001 :: 1 = #0001 = 0000000000000001
+ END
-DIV START ; 減算を用いた 32 ビット除算
- PUSH 0,GR6
- PUSH 0,GR7
- LD GR6,GR1
- LD GR7,GR2
- LD GR1,=#FFFF ; 商の初期化
- LD GR2,=#FFFF
- LP LD GR4,GR6
- LD GR5,GR7
- ADDL GR2,=1 ; 商のカウントアップ
- JOV ADJ1
- JUMP CONT
- ADJ1
- CONT SUBL GR6,0,GR3
- J0V FIN
- SUBL GR7,1,GR3
-
- JUMP LP
- ADJ2 SUBL GR6,=1
- J0V FIN
- JUMP LP
- FIN POP GR7
- POP GR6
- RET
- END
-
+DIV START ; 減算を用いた32ビット除算
+ PUSH 0,GR6
+ PUSH 0,GR7
+ LD GR6,GR1
+ LD GR7,GR2
+ LD GR1,=#FFFF ; 商の初期化
+ LD GR2,=#FFFF
+LP LD GR4,GR6
+ LD GR5,GR7
+ ADDL GR2,=1 ; 商のカウントアップ
+ JOV ADJ1
+ JUMP CONT
+ADJ1 ADDL GR1,=1
+CONT SUBL GR6,0,GR3
+ JOV FIN
+ SUBL GR7,1,GR3
+ JOV ADJ2
+ JUMP LP
+ADJ2 SUBL GR6,=1
+ JOV FIN
+ JUMP LP
+FIN POP GR7
+ POP GR6
+ RET
+ END
+
bool disassemble(const char *file)
{
- FILE *fp;
bool stat = true;
- int i = 0;
- WORD w, cmd, r, x, r1, r2, adr;
- CMDTYPE type = 0;
+ FILE *fp;
+ WORD i = 0, w, cmd, r, x, r1, r2, adr;
+ CMDTYPE cmdtype = 0;
char *cmdname;
assert(file != NULL);
create_code_cmdtype(); /* 命令のコードとタイプがキーのハッシュ表を作成 */
fprintf(stdout, "MAIN\tSTART\n");
- for( ; !feof(fp); ) {
+ for(; ;) {
fread(&w, sizeof(WORD), 1, fp);
+ if(feof(fp)) {
+ break;
+ }
cmd = w & 0xFF00;
cmdname = getcmdname(cmd);
+ cmdtype = getcmdtype(cmd);
if(cmd == 0xFF00 || (w != 0 && cmd == 0x0000)) {
- fprintf(stdout, "\tDC\t%d\t\t; #%04X", w, i++);
- } else if((type = getcmdtype(cmd)) == R_ADR_X || type == ADR_X) {
+ fprintf(stdout, "\tDC\t%d\t\t\t\t; #%04X: #%04X :: ", w, i++, w);
+ print_dumpword(w, true);
+ } else if(cmdtype == R_ADR_X || cmdtype == ADR_X) {
fread(&adr, sizeof(WORD), 1, fp);
fprintf(stdout, "\t%s\t", cmdname);
- if(type == R_ADR_X) {
- r = (w & 0x00F0) >> 4;
+ if(cmdtype == R_ADR_X) {
+ r = (w & 0x00F0) >> 4;
fprintf(stdout, "%s,", grstr(r));
}
fprintf(stdout, "#%04X", adr);
- if((x = w & 0x000F) != 0) {
+ if((x = w & 0x000F) != 0) {
fprintf(stdout, ",%s", grstr(x));
}
- fprintf(stdout, "\t\t; #%04X", i);
+ fprintf(stdout, "\t\t\t\t; #%04X: #%04X #%04X", i, w, adr);
i += 2;
} else {
fprintf(stdout, "\t%s", cmdname);
- if(type == R1_R2) {
- r1 = (w & 0x00F0) >> 4;
- r2 = w & 0x000F;
+ if(cmdtype == R1_R2) {
+ r1 = (w & 0x00F0) >> 4;
+ r2 = w & 0x000F;
fprintf(stdout, "\t%s,%s", grstr(r1), grstr(r2));
- } else if(type == R_) {
+ } else if(cmdtype == R_) {
r = (w & 0x00F0) >> 4;
fprintf(stdout, "\t%s", grstr(r));
}
- fprintf(stdout, "\t\t; #%04X", i++);
+ fprintf(stdout, "\t\t\t\t; #%04X: #%04X", i++, w);
}
fprintf(stdout, "\n");
}
fprintf(stdout, "\tEND\n");
free_code_cmdtype();
+ fclose(fp);
return stat;
}
for(i = 0; i < GRSIZE; i++ ) {
fprintf(stdout, "#%04X: GR%d: ", sys->cpu->pr, i);
print_dumpword(sys->cpu->gr[i], (&execmode)->logical);
+ fprintf(stdout, "\n");
}
fprintf(stdout, "#%04X: SP: %6d = #%04X = %s\n",
sys->cpu->pr, sys->cpu->sp, sys->cpu->sp, sp = word2bit(sys->cpu->sp));
}
fprintf(stdout, "%6s: ", argv[optind]);
print_dumpword(word, logicalmode);
+ fprintf(stdout, "\n");
return 0;
}
sys->cpu->pr += 1;
}
-void addl(WORD r, WORD val)
+void addl_subl_flagset(long val)
{
- long tmp;
sys->cpu->fr = 0x0;
- if((tmp = sys->cpu->gr[r] + val) < 0 || tmp > 65535) {
+ if(val > 65535) {
sys->cpu->fr += OF;
}
- if(((sys->cpu->gr[r] = (WORD)(tmp & 0xFFFF)) & 0x8000) == 0x8000) {
+ if(((WORD)(val) & 0x8000) == 0x8000) {
sys->cpu->fr += SF;
- } else if(sys->cpu->gr[r] == 0x0) {
+ } else if(val == 0x0) {
sys->cpu->fr += ZF;
}
}
+void addl(WORD r, WORD val)
+{
+ long s;
+
+ s = sys->cpu->gr[r] + val;
+ sys->cpu->gr[r] = (WORD)s;
+ addl_subl_flagset(s);
+}
+
+void subl(WORD r, WORD val)
+{
+ long s;
+
+ if((s = sys->cpu->gr[r] + (~val + 1)) > 0x10000) {
+ s -= 0x10000;
+ }
+ sys->cpu->gr[r] = (WORD)s;
+ addl_subl_flagset(s);
+ if(r < val) {
+ sys->cpu->fr += OF;
+ }
+}
+
void addl_r_adr_x()
{
WORD w[2];
WORD w[2];
w[0] = sys->memory[sys->cpu->pr];
w[1] = sys->memory[sys->cpu->pr + 1];
- addl(get_r_r1(w[0]), ~(get_val_adr_x(w[1], w[0])) + 1);
+ subl(get_r_r1(w[0]), (get_val_adr_x(w[1], w[0])));
sys->cpu->pr += 2;
}
{
WORD w[1];
w[0] = sys->memory[sys->cpu->pr];
- addl(get_r_r1(w[0]), ~(sys->cpu->gr[get_x_r2(w[0])]) + 1);
+ subl(get_r_r1(w[0]), (sys->cpu->gr[get_x_r2(w[0])]));
sys->cpu->pr += 1;
}
} else if(word == '\t') {
fprintf(stdout, " = \'\\t\'");
}
- fprintf(stdout, "\n");
FREE(b);
}
# 複数の子ディレクトリーでmakeを実行
-CMD = casl2_smoke casl2_opt casl2_cmd casl2_err casl2_lib comet2_smoke comet2_opt comet2_cmd comet2_err comet2_lib dumpword
+CMD = casl2_smoke casl2_opt casl2_cmd casl2_err casl2_lib comet2_smoke comet2_opt comet2_cmd comet2_err comet2_lib disassemble dumpword
define make_dirs
$(foreach d,$1,$(MAKE) -sC $d $2)
endef
-;;; ADDL r,adr 演算結果が負数(r < adr)
+;;; ADDL r,adr
MAIN START
LD GR1,A
ADDL GR1,B
Assemble ../../../../as/cmd/ADDL/addl_r_adr__as1.casl (0)
Assemble ../../../../as/cmd/ADDL/addl_r_adr__as1.casl (1)
-../../../../as/cmd/ADDL/addl_r_adr__as1.casl: 1:;;; ADDL r,adr 演算結果が負数(r < adr)
+../../../../as/cmd/ADDL/addl_r_adr__as1.casl: 1:;;; ADDL r,adr
../../../../as/cmd/ADDL/addl_r_adr__as1.casl: 2:MAIN START
../../../../as/cmd/ADDL/addl_r_adr__as1.casl: 3: LD GR1,A
#0000 #1010
#0000: 0000: 1010 0005 2210 0006 8100 FFEC 000A 0000
#0002: Register::::
#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: -20 = #FFEC = 1111111111101100
+#0002: GR1: 65516 = #FFEC = 1111111111101100
#0002: GR2: 0 = #0000 = 0000000000000000
#0002: GR3: 0 = #0000 = 0000000000000000
#0002: GR4: 0 = #0000 = 0000000000000000
#0002: 0000: 1010 0005 2210 0006 8100 FFEC 000A 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: -10 = #FFF6 = 1111111111110110
+#0004: GR1: 65526 = #FFF6 = 1111111111110110
#0004: GR2: 0 = #0000 = 0000000000000000
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 010
+#0004: FR (OF SF ZF): 110
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2210 0006 8100 FFEC 000A 0000
cat ../../../../as/cmd/ADDL/addl_r_adr__as1.casl
-../../../../casl2 -atd -M8 ../../../../as/cmd/ADDL/addl_r_adr__as1.casl
+../../../../casl2 -aTd -M8 ../../../../as/cmd/ADDL/addl_r_adr__as1.casl
LD GR1,A
ADDL GR1,B
RET
-A DC #FFF6 ; -10
+A DC #FFF6 ; 65526
B DC 10
END
#0003 #0006
../../../../as/cmd/ADDL/addl_r_adr__az.casl: 5: RET
#0004 #8100
-../../../../as/cmd/ADDL/addl_r_adr__az.casl: 6:A DC #FFF6 ; -10
+../../../../as/cmd/ADDL/addl_r_adr__az.casl: 6:A DC #FFF6 ; 65526
#0005 #FFF6
../../../../as/cmd/ADDL/addl_r_adr__az.casl: 7:B DC 10
#0006 #000A
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 101
+#0004: FR (OF SF ZF): 100
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2210 0006 8100 FFF6 000A 0000
#0005: GR7: 0 = #0000 = 0000000000000000
#0005: SP: 16 = #0010 = 0000000000010000
#0005: PR: 5 = #0005 = 0000000000000101
-#0005: FR (OF SF ZF): 100
+#0005: FR (OF SF ZF): 000
#0005: Memory::::
#0005: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
#0005: 0000: 1010 0006 1020 0007 2712 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000 0000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 100
+#0004: FR (OF SF ZF): 000
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 0003 0001 0000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 010
+#0004: FR (OF SF ZF): 110
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 7FFE FFF6 0000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 010
+#0004: FR (OF SF ZF): 110
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 000A 0014 0000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 010
+#0004: FR (OF SF ZF): 110
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 0002 000F 0000
-;;; SUBL r,adr オーバーフロー
+;;; SUBL r,adr 算術減算ではオーバーフロー、論理演算ではオーバーフローなし
MAIN START
LD GR1,A
SUBL GR1,B
RET
-A DC #8002 ; -32766
+A DC #8002 ; 32770
B DC #7FFF ; 32767
END
Assemble ../../../../as/cmd/SUBL/subl_r_adr__o.casl (0)
Assemble ../../../../as/cmd/SUBL/subl_r_adr__o.casl (1)
-../../../../as/cmd/SUBL/subl_r_adr__o.casl: 1:;;; SUBL r,adr オーバーフロー
+../../../../as/cmd/SUBL/subl_r_adr__o.casl: 1:;;; SUBL r,adr 算術減算ではオーバーフロー、論理演算ではオーバーフローなし
../../../../as/cmd/SUBL/subl_r_adr__o.casl: 2:MAIN START
../../../../as/cmd/SUBL/subl_r_adr__o.casl: 3: LD GR1,A
#0000 #1010
#0003 #0006
../../../../as/cmd/SUBL/subl_r_adr__o.casl: 5: RET
#0004 #8100
-../../../../as/cmd/SUBL/subl_r_adr__o.casl: 6:A DC #8002 ; -32766
+../../../../as/cmd/SUBL/subl_r_adr__o.casl: 6:A DC #8002 ; 32770
#0005 #8002
../../../../as/cmd/SUBL/subl_r_adr__o.casl: 7:B DC #7FFF ; 32767
#0006 #7FFF
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 100
+#0004: FR (OF SF ZF): 000
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 8002 7FFF 0000
#0004: GR7: 0 = #0000 = 0000000000000000
#0004: SP: 8 = #0008 = 0000000000001000
#0004: PR: 4 = #0004 = 0000000000000100
-#0004: FR (OF SF ZF): 101
+#0004: FR (OF SF ZF): 001
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007
#0004: 0000: 1010 0005 2310 0006 8100 FFF6 FFF6 0000
LAD GR2,1
SUBL GR1,A,GR2
RET
-A DC 3
- DC 1
+A DC 5
+ DC 2
END
Assemble ../../../../as/cmd/SUBL/subl_r_adr_x.casl (0)
#0005 #0007
../../../../as/cmd/SUBL/subl_r_adr_x.casl: 6: RET
#0006 #8100
-../../../../as/cmd/SUBL/subl_r_adr_x.casl: 7:A DC 3
- #0007 #0003
-../../../../as/cmd/SUBL/subl_r_adr_x.casl: 8: DC 1
- #0008 #0001
+../../../../as/cmd/SUBL/subl_r_adr_x.casl: 7:A DC 5
+ #0007 #0005
+../../../../as/cmd/SUBL/subl_r_adr_x.casl: 8: DC 2
+ #0008 #0002
../../../../as/cmd/SUBL/subl_r_adr_x.casl: 9: END
Executing machine codes
#0000: FR (OF SF ZF): 000
#0000: Memory::::
#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0000: 0000: 1010 0007 1220 0001 2312 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
+#0000: 0000: 1010 0007 1220 0001 2312 0007 8100 0005 0002 0000 0000 0000 0000 0000 0000 0000
#0002: Register::::
#0002: GR0: 0 = #0000 = 0000000000000000
-#0002: GR1: 3 = #0003 = 0000000000000011
+#0002: GR1: 5 = #0005 = 0000000000000101
#0002: GR2: 0 = #0000 = 0000000000000000
#0002: GR3: 0 = #0000 = 0000000000000000
#0002: GR4: 0 = #0000 = 0000000000000000
#0002: FR (OF SF ZF): 000
#0002: Memory::::
#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0002: 0000: 1010 0007 1220 0001 2312 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
+#0002: 0000: 1010 0007 1220 0001 2312 0007 8100 0005 0002 0000 0000 0000 0000 0000 0000 0000
#0004: Register::::
#0004: GR0: 0 = #0000 = 0000000000000000
-#0004: GR1: 3 = #0003 = 0000000000000011
+#0004: GR1: 5 = #0005 = 0000000000000101
#0004: GR2: 1 = #0001 = 0000000000000001
#0004: GR3: 0 = #0000 = 0000000000000000
#0004: GR4: 0 = #0000 = 0000000000000000
#0004: FR (OF SF ZF): 000
#0004: Memory::::
#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0004: 0000: 1010 0007 1220 0001 2312 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
+#0004: 0000: 1010 0007 1220 0001 2312 0007 8100 0005 0002 0000 0000 0000 0000 0000 0000 0000
#0006: Register::::
#0006: GR0: 0 = #0000 = 0000000000000000
-#0006: GR1: 2 = #0002 = 0000000000000010
+#0006: GR1: 3 = #0003 = 0000000000000011
#0006: GR2: 1 = #0001 = 0000000000000001
#0006: GR3: 0 = #0000 = 0000000000000000
#0006: GR4: 0 = #0000 = 0000000000000000
#0006: GR7: 0 = #0000 = 0000000000000000
#0006: SP: 16 = #0010 = 0000000000010000
#0006: PR: 6 = #0006 = 0000000000000110
-#0006: FR (OF SF ZF): 100
+#0006: FR (OF SF ZF): 000
#0006: Memory::::
#0006: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
-#0006: 0000: 1010 0007 1220 0001 2312 0007 8100 0003 0001 0000 0000 0000 0000 0000 0000 0000
+#0006: 0000: 1010 0007 1220 0001 2312 0007 8100 0005 0002 0000 0000 0000 0000 0000 0000 0000
MAIN START
- PUSH #0000,GR1 ; #0000
- LAD GR0,#0000 ; #0002
- LD GR1,#0011 ; #0004
- ADDL GR0,GR1 ; #0006
- ADDL GR1,#0013 ; #0007
- CPL GR1,#0012 ; #0009
- JPL #000F ; #000B
- JUMP #0006 ; #000D
- POP GR1 ; #000F
- RET ; #0010
- DC 1 ; #0011
- DC 10 ; #0012
- DC 1 ; #0013
- DC 1 ; #0014
+ PUSH #0000,GR1 ; #0000: #7001 #0000
+ LAD GR0,#0000 ; #0002: #1200 #0000
+ LD GR1,#0011 ; #0004: #1010 #0011
+ ADDL GR0,GR1 ; #0006: #2601
+ ADDL GR1,#0013 ; #0007: #2210 #0013
+ CPL GR1,#0012 ; #0009: #4110 #0012
+ JPL #000F ; #000B: #6500 #000F
+ JUMP #0006 ; #000D: #6400 #0006
+ POP GR1 ; #000F: #7110
+ RET ; #0010: #8100
+ DC 1 ; #0011: #0001 :: 1 = #0001 = 0000000000000001
+ DC 10 ; #0012: #000A :: 10 = #000A = 0000000000001010 = '\n'
+ DC 1 ; #0013: #0001 :: 1 = #0001 = 0000000000000001
END