--- /dev/null
+MAIN START
+ LAD GR2,ADR1
+ LD GR1,ADR0
+ RET
+ADR0 DC ADR1
+ADR1 DC 13
+ END
+ADR1 START
+ LAD GR2,29
+ RET
+ END
--- /dev/null
+MAIN START
+ LAD GR1,ADR1
+ LD GR2,ADR2
+ RET
+ADR1 DC 21
+ADR2 DC ADR1
+ END
--- /dev/null
+MAIN START
+ LAD GR2,ADR2
+ LD GR1,ADR1
+ RET
+ADR1 DC ADR2
+ END
+ADR2 START
+ LAD GR2,29
+ RET
+ END
} else {
if(pass == SECOND) {
if((adr = getlabel(prog, str)) == 0xFFFF) {
- setcerr(103, str); /* label not found */
+ adr = getlabel("", str);
+ }
+ if(adr == 0xFFFF) {
+ setcerr(103, str); /* label not found */ setcerr(103, str); /* label not found */
}
}
}
adr = nh2word(str);
} else {
if(pass == SECOND && (adr = getlabel(asptr->prog, str)) == 0xFFFF) {
+ adr = getlabel("", str);
+ }
+ if(pass == SECOND && adr == 0xFFFF) {
setcerr(103, str); /* label not found */
}
}
--- /dev/null
+
+Assemble ../../../../as/cmd/DC/dc__label_both.casl (0)
+
+Assemble ../../../../as/cmd/DC/dc__label_both.casl (1)
+../../../../as/cmd/DC/dc__label_both.casl: 1:MAIN START
+../../../../as/cmd/DC/dc__label_both.casl: 2: LAD GR2,ADR1
+ #0000 #1220
+ #0001 #0006
+../../../../as/cmd/DC/dc__label_both.casl: 3: LD GR1,ADR0
+ #0002 #1010
+ #0003 #0005
+../../../../as/cmd/DC/dc__label_both.casl: 4: RET
+ #0004 #8100
+../../../../as/cmd/DC/dc__label_both.casl: 5:ADR0 DC ADR1
+ #0005 #0006
+../../../../as/cmd/DC/dc__label_both.casl: 6:ADR1 DC 13
+ #0006 #000D
+../../../../as/cmd/DC/dc__label_both.casl: 7: END
+../../../../as/cmd/DC/dc__label_both.casl: 8:ADR1 START
+../../../../as/cmd/DC/dc__label_both.casl: 9: LAD GR2,29
+ #0007 #1220
+ #0008 #001D
+../../../../as/cmd/DC/dc__label_both.casl: 10: RET
+ #0009 #8100
+../../../../as/cmd/DC/dc__label_both.casl: 11: END
+
+Executing machine codes
+#0000: Register::::
+#0000: GR0: 0 = #0000 = 0000000000000000
+#0000: GR1: 0 = #0000 = 0000000000000000
+#0000: GR2: 0 = #0000 = 0000000000000000
+#0000: GR3: 0 = #0000 = 0000000000000000
+#0000: GR4: 0 = #0000 = 0000000000000000
+#0000: GR5: 0 = #0000 = 0000000000000000
+#0000: GR6: 0 = #0000 = 0000000000000000
+#0000: GR7: 0 = #0000 = 0000000000000000
+#0000: SP: 16 = #0010 = 0000000000010000
+#0000: PR: 0 = #0000 = 0000000000000000
+#0000: FR (OF SF ZF): 000
+#0000: Memory::::
+#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+ -------------------------------------------------------------------------------------
+#0000: 0000: 1220 0006 1010 0005 8100 0006 000D 1220 001D 8100 0000 0000 0000 0000 0000 0000
+
+#0002: Register::::
+#0002: GR0: 0 = #0000 = 0000000000000000
+#0002: GR1: 0 = #0000 = 0000000000000000
+#0002: GR2: 6 = #0006 = 0000000000000110
+#0002: GR3: 0 = #0000 = 0000000000000000
+#0002: GR4: 0 = #0000 = 0000000000000000
+#0002: GR5: 0 = #0000 = 0000000000000000
+#0002: GR6: 0 = #0000 = 0000000000000000
+#0002: GR7: 0 = #0000 = 0000000000000000
+#0002: SP: 16 = #0010 = 0000000000010000
+#0002: PR: 2 = #0002 = 0000000000000010
+#0002: FR (OF SF ZF): 000
+#0002: Memory::::
+#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+ -------------------------------------------------------------------------------------
+#0002: 0000: 1220 0006 1010 0005 8100 0006 000D 1220 001D 8100 0000 0000 0000 0000 0000 0000
+
+#0004: Register::::
+#0004: GR0: 0 = #0000 = 0000000000000000
+#0004: GR1: 6 = #0006 = 0000000000000110
+#0004: GR2: 6 = #0006 = 0000000000000110
+#0004: GR3: 0 = #0000 = 0000000000000000
+#0004: GR4: 0 = #0000 = 0000000000000000
+#0004: GR5: 0 = #0000 = 0000000000000000
+#0004: GR6: 0 = #0000 = 0000000000000000
+#0004: GR7: 0 = #0000 = 0000000000000000
+#0004: SP: 16 = #0010 = 0000000000010000
+#0004: PR: 4 = #0004 = 0000000000000100
+#0004: FR (OF SF ZF): 000
+#0004: Memory::::
+#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+ -------------------------------------------------------------------------------------
+#0004: 0000: 1220 0006 1010 0005 8100 0006 000D 1220 001D 8100 0000 0000 0000 0000 0000 0000
+
--- /dev/null
+include ../Define.mk
+include ../Test.mk
--- /dev/null
+../../../../casl2 -atd -M16 ../../../../as/cmd/DC/dc__label_both.casl
--- /dev/null
+
+Assemble ../../../../as/cmd/DC/dc__label_inner.casl (0)
+
+Assemble ../../../../as/cmd/DC/dc__label_inner.casl (1)
+../../../../as/cmd/DC/dc__label_inner.casl: 1:MAIN START
+../../../../as/cmd/DC/dc__label_inner.casl: 2: LAD GR1,ADR1
+ #0000 #1210
+ #0001 #0005
+../../../../as/cmd/DC/dc__label_inner.casl: 3: LD GR2,ADR2
+ #0002 #1020
+ #0003 #0006
+../../../../as/cmd/DC/dc__label_inner.casl: 4: RET
+ #0004 #8100
+../../../../as/cmd/DC/dc__label_inner.casl: 5:ADR1 DC 21
+ #0005 #0015
+../../../../as/cmd/DC/dc__label_inner.casl: 6:ADR2 DC ADR1
+ #0006 #0005
+../../../../as/cmd/DC/dc__label_inner.casl: 7: END
+
+Executing machine codes
+#0000: Register::::
+#0000: GR0: 0 = #0000 = 0000000000000000
+#0000: GR1: 0 = #0000 = 0000000000000000
+#0000: GR2: 0 = #0000 = 0000000000000000
+#0000: GR3: 0 = #0000 = 0000000000000000
+#0000: GR4: 0 = #0000 = 0000000000000000
+#0000: GR5: 0 = #0000 = 0000000000000000
+#0000: GR6: 0 = #0000 = 0000000000000000
+#0000: GR7: 0 = #0000 = 0000000000000000
+#0000: SP: 32 = #0020 = 0000000000100000
+#0000: PR: 0 = #0000 = 0000000000000000
+#0000: FR (OF SF ZF): 000
+#0000: Memory::::
+#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+ -------------------------------------------------------------------------------------
+#0000: 0000: 1210 0005 1020 0006 8100 0015 0005 0000 0000 0000 0000 0000 0000 0000 0000 0000
+#0000: 0010: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
+
+#0002: Register::::
+#0002: GR0: 0 = #0000 = 0000000000000000
+#0002: GR1: 5 = #0005 = 0000000000000101
+#0002: GR2: 0 = #0000 = 0000000000000000
+#0002: GR3: 0 = #0000 = 0000000000000000
+#0002: GR4: 0 = #0000 = 0000000000000000
+#0002: GR5: 0 = #0000 = 0000000000000000
+#0002: GR6: 0 = #0000 = 0000000000000000
+#0002: GR7: 0 = #0000 = 0000000000000000
+#0002: SP: 32 = #0020 = 0000000000100000
+#0002: PR: 2 = #0002 = 0000000000000010
+#0002: FR (OF SF ZF): 000
+#0002: Memory::::
+#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+ -------------------------------------------------------------------------------------
+#0002: 0000: 1210 0005 1020 0006 8100 0015 0005 0000 0000 0000 0000 0000 0000 0000 0000 0000
+#0002: 0010: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
+
+#0004: Register::::
+#0004: GR0: 0 = #0000 = 0000000000000000
+#0004: GR1: 5 = #0005 = 0000000000000101
+#0004: GR2: 5 = #0005 = 0000000000000101
+#0004: GR3: 0 = #0000 = 0000000000000000
+#0004: GR4: 0 = #0000 = 0000000000000000
+#0004: GR5: 0 = #0000 = 0000000000000000
+#0004: GR6: 0 = #0000 = 0000000000000000
+#0004: GR7: 0 = #0000 = 0000000000000000
+#0004: SP: 32 = #0020 = 0000000000100000
+#0004: PR: 4 = #0004 = 0000000000000100
+#0004: FR (OF SF ZF): 000
+#0004: Memory::::
+#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+ -------------------------------------------------------------------------------------
+#0004: 0000: 1210 0005 1020 0006 8100 0015 0005 0000 0000 0000 0000 0000 0000 0000 0000 0000
+#0004: 0010: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
+
--- /dev/null
+include ../Define.mk
+include ../Test.mk
--- /dev/null
+../../../../casl2 -atd -M32 ../../../../as/cmd/DC/dc__label_inner.casl
--- /dev/null
+
+Assemble ../../../../as/cmd/DC/dc__label_outer.casl (0)
+
+Assemble ../../../../as/cmd/DC/dc__label_outer.casl (1)
+../../../../as/cmd/DC/dc__label_outer.casl: 1:MAIN START
+../../../../as/cmd/DC/dc__label_outer.casl: 2: LAD GR2,ADR2
+ #0000 #1220
+ #0001 #0006
+../../../../as/cmd/DC/dc__label_outer.casl: 3: LD GR1,ADR1
+ #0002 #1010
+ #0003 #0005
+../../../../as/cmd/DC/dc__label_outer.casl: 4: RET
+ #0004 #8100
+../../../../as/cmd/DC/dc__label_outer.casl: 5:ADR1 DC ADR2
+ #0005 #0006
+../../../../as/cmd/DC/dc__label_outer.casl: 6: END
+../../../../as/cmd/DC/dc__label_outer.casl: 7:ADR2 START
+../../../../as/cmd/DC/dc__label_outer.casl: 8: LAD GR2,29
+ #0006 #1220
+ #0007 #001D
+../../../../as/cmd/DC/dc__label_outer.casl: 9: RET
+ #0008 #8100
+../../../../as/cmd/DC/dc__label_outer.casl: 10: END
+
+Executing machine codes
+#0000: Register::::
+#0000: GR0: 0 = #0000 = 0000000000000000
+#0000: GR1: 0 = #0000 = 0000000000000000
+#0000: GR2: 0 = #0000 = 0000000000000000
+#0000: GR3: 0 = #0000 = 0000000000000000
+#0000: GR4: 0 = #0000 = 0000000000000000
+#0000: GR5: 0 = #0000 = 0000000000000000
+#0000: GR6: 0 = #0000 = 0000000000000000
+#0000: GR7: 0 = #0000 = 0000000000000000
+#0000: SP: 32 = #0020 = 0000000000100000
+#0000: PR: 0 = #0000 = 0000000000000000
+#0000: FR (OF SF ZF): 000
+#0000: Memory::::
+#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+ -------------------------------------------------------------------------------------
+#0000: 0000: 1220 0006 1010 0005 8100 0006 1220 001D 8100 0000 0000 0000 0000 0000 0000 0000
+#0000: 0010: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
+
+#0002: Register::::
+#0002: GR0: 0 = #0000 = 0000000000000000
+#0002: GR1: 0 = #0000 = 0000000000000000
+#0002: GR2: 6 = #0006 = 0000000000000110
+#0002: GR3: 0 = #0000 = 0000000000000000
+#0002: GR4: 0 = #0000 = 0000000000000000
+#0002: GR5: 0 = #0000 = 0000000000000000
+#0002: GR6: 0 = #0000 = 0000000000000000
+#0002: GR7: 0 = #0000 = 0000000000000000
+#0002: SP: 32 = #0020 = 0000000000100000
+#0002: PR: 2 = #0002 = 0000000000000010
+#0002: FR (OF SF ZF): 000
+#0002: Memory::::
+#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+ -------------------------------------------------------------------------------------
+#0002: 0000: 1220 0006 1010 0005 8100 0006 1220 001D 8100 0000 0000 0000 0000 0000 0000 0000
+#0002: 0010: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
+
+#0004: Register::::
+#0004: GR0: 0 = #0000 = 0000000000000000
+#0004: GR1: 6 = #0006 = 0000000000000110
+#0004: GR2: 6 = #0006 = 0000000000000110
+#0004: GR3: 0 = #0000 = 0000000000000000
+#0004: GR4: 0 = #0000 = 0000000000000000
+#0004: GR5: 0 = #0000 = 0000000000000000
+#0004: GR6: 0 = #0000 = 0000000000000000
+#0004: GR7: 0 = #0000 = 0000000000000000
+#0004: SP: 32 = #0020 = 0000000000100000
+#0004: PR: 4 = #0004 = 0000000000000100
+#0004: FR (OF SF ZF): 000
+#0004: Memory::::
+#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+ -------------------------------------------------------------------------------------
+#0004: 0000: 1220 0006 1010 0005 8100 0006 1220 001D 8100 0000 0000 0000 0000 0000 0000 0000
+#0004: 0010: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
+
--- /dev/null
+include ../Define.mk
+include ../Test.mk
--- /dev/null
+../../../../casl2 -atd -M32 ../../../../as/cmd/DC/dc__label_outer.casl