--- /dev/null
+;;; ST r,adr,x
+MAIN START
+ LD GR1,A
+ LAD GR2,A
+ ST GR1,1,GR2
+ RET
+A DC 5
+B DS 1
+ END
+
+Assemble ../../../../as/cmd/ST/st1.casl (0)
+
+Assemble ../../../../as/cmd/ST/st1.casl (1)
+../../../../as/cmd/ST/st1.casl: 1:;;; ST r,adr,x
+../../../../as/cmd/ST/st1.casl: 2:MAIN START
+../../../../as/cmd/ST/st1.casl: 3: LD GR1,A
+ #0000 #1010
+ #0001 #0007
+../../../../as/cmd/ST/st1.casl: 4: LAD GR2,A
+ #0002 #1220
+ #0003 #0007
+../../../../as/cmd/ST/st1.casl: 5: ST GR1,1,GR2
+ #0004 #1112
+ #0005 #0001
+../../../../as/cmd/ST/st1.casl: 6: RET
+ #0006 #8100
+../../../../as/cmd/ST/st1.casl: 7:A DC 5
+ #0007 #0005
+../../../../as/cmd/ST/st1.casl: 8:B DS 1
+ #0008 #0000
+../../../../as/cmd/ST/st1.casl: 9: END
+
+Executing machine codes
+#0000: Register::::
+#0000: GR0: 0 = #0000 = 0000000000000000
+#0000: GR1: 0 = #0000 = 0000000000000000
+#0000: GR2: 0 = #0000 = 0000000000000000
+#0000: GR3: 0 = #0000 = 0000000000000000
+#0000: GR4: 0 = #0000 = 0000000000000000
+#0000: GR5: 0 = #0000 = 0000000000000000
+#0000: GR6: 0 = #0000 = 0000000000000000
+#0000: GR7: 0 = #0000 = 0000000000000000
+#0000: SP: 16 = #0010 = 0000000000010000
+#0000: PR: 0 = #0000 = 0000000000000000
+#0000: FR (OF SF ZF): 000
+#0000: Memory::::
+#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+#0000: 0000: 1010 0007 1220 0007 1112 0001 8100 0005 0000 0000 0000 0000 0000 0000 0000 0000
+
+#0002: Register::::
+#0002: GR0: 0 = #0000 = 0000000000000000
+#0002: GR1: 5 = #0005 = 0000000000000101
+#0002: GR2: 0 = #0000 = 0000000000000000
+#0002: GR3: 0 = #0000 = 0000000000000000
+#0002: GR4: 0 = #0000 = 0000000000000000
+#0002: GR5: 0 = #0000 = 0000000000000000
+#0002: GR6: 0 = #0000 = 0000000000000000
+#0002: GR7: 0 = #0000 = 0000000000000000
+#0002: SP: 16 = #0010 = 0000000000010000
+#0002: PR: 2 = #0002 = 0000000000000010
+#0002: FR (OF SF ZF): 000
+#0002: Memory::::
+#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+#0002: 0000: 1010 0007 1220 0007 1112 0001 8100 0005 0000 0000 0000 0000 0000 0000 0000 0000
+
+#0004: Register::::
+#0004: GR0: 0 = #0000 = 0000000000000000
+#0004: GR1: 5 = #0005 = 0000000000000101
+#0004: GR2: 7 = #0007 = 0000000000000111
+#0004: GR3: 0 = #0000 = 0000000000000000
+#0004: GR4: 0 = #0000 = 0000000000000000
+#0004: GR5: 0 = #0000 = 0000000000000000
+#0004: GR6: 0 = #0000 = 0000000000000000
+#0004: GR7: 0 = #0000 = 0000000000000000
+#0004: SP: 16 = #0010 = 0000000000010000
+#0004: PR: 4 = #0004 = 0000000000000100
+#0004: FR (OF SF ZF): 000
+#0004: Memory::::
+#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+#0004: 0000: 1010 0007 1220 0007 1112 0001 8100 0005 0000 0000 0000 0000 0000 0000 0000 0000
+
+#0006: Register::::
+#0006: GR0: 0 = #0000 = 0000000000000000
+#0006: GR1: 5 = #0005 = 0000000000000101
+#0006: GR2: 7 = #0007 = 0000000000000111
+#0006: GR3: 0 = #0000 = 0000000000000000
+#0006: GR4: 0 = #0000 = 0000000000000000
+#0006: GR5: 0 = #0000 = 0000000000000000
+#0006: GR6: 0 = #0000 = 0000000000000000
+#0006: GR7: 0 = #0000 = 0000000000000000
+#0006: SP: 16 = #0010 = 0000000000010000
+#0006: PR: 6 = #0006 = 0000000000000110
+#0006: FR (OF SF ZF): 000
+#0006: Memory::::
+#0006: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+#0006: 0000: 1010 0007 1220 0007 1112 0001 8100 0005 0005 0000 0000 0000 0000 0000 0000 0000
+