コマンドテストの刷新

[YACASL2.git] / test / integration / casl2 / cmd_ADDL_addl0_as1 / 0.txt

diff --git a/test/integration/casl2/cmd_ADDL_addl0_as1/0.txt b/test/integration/casl2/cmd_ADDL_addl0_as1/0.txt
new file mode 100644 (file)
index 0000000..34ef281
--- /dev/null
+++ b/test/integration/casl2/cmd_ADDL_addl0_as1/0.txt
@@ -0,0 +1,67 @@
+../../../../casl2 -atd -M8 ../../../../as/cmd/ADDL/addl0_as1.casl
+
+Assemble ../../../../as/cmd/ADDL/addl0_as1.casl (0)
+
+Assemble ../../../../as/cmd/ADDL/addl0_as1.casl (1)
+../../../../as/cmd/ADDL/addl0_as1.casl:    1:;;; ADDL r,adr 演算結果が負数(r < adr)
+../../../../as/cmd/ADDL/addl0_as1.casl:    2:MAIN    START
+../../../../as/cmd/ADDL/addl0_as1.casl:    3:        LD      GR1,A
+       #0000   #1010
+       #0001   #0005
+../../../../as/cmd/ADDL/addl0_as1.casl:    4:        ADDL    GR1,B
+       #0002   #2210
+       #0003   #0006
+../../../../as/cmd/ADDL/addl0_as1.casl:    5:        RET
+       #0004   #8100
+../../../../as/cmd/ADDL/addl0_as1.casl:    6:A       DC      #FFEC           ; -20
+       #0005   #FFEC
+../../../../as/cmd/ADDL/addl0_as1.casl:    7:B       DC      #000A           ; 10
+       #0006   #000A
+../../../../as/cmd/ADDL/addl0_as1.casl:    8:        END
+
+Executing machine codes
+#0000: Register::::
+#0000: GR0:      0 = #0000 = 0000000000000000
+#0000: GR1:      0 = #0000 = 0000000000000000
+#0000: GR2:      0 = #0000 = 0000000000000000
+#0000: GR3:      0 = #0000 = 0000000000000000
+#0000: GR4:      0 = #0000 = 0000000000000000
+#0000: GR5:      0 = #0000 = 0000000000000000
+#0000: GR6:      0 = #0000 = 0000000000000000
+#0000: GR7:      0 = #0000 = 0000000000000000
+#0000: SP:       8 = #0008 = 0000000000001000
+#0000: PR:       0 = #0000 = 0000000000000000
+#0000: FR (OF SF ZF): 000
+#0000: Memory::::
+#0000: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+#0000: 0000: 1010 0005 2210 0006 8100 FFEC 000A 0000 
+#0002: Register::::
+#0002: GR0:      0 = #0000 = 0000000000000000
+#0002: GR1:    -20 = #FFEC = 1111111111101100
+#0002: GR2:      0 = #0000 = 0000000000000000
+#0002: GR3:      0 = #0000 = 0000000000000000
+#0002: GR4:      0 = #0000 = 0000000000000000
+#0002: GR5:      0 = #0000 = 0000000000000000
+#0002: GR6:      0 = #0000 = 0000000000000000
+#0002: GR7:      0 = #0000 = 0000000000000000
+#0002: SP:       8 = #0008 = 0000000000001000
+#0002: PR:       2 = #0002 = 0000000000000010
+#0002: FR (OF SF ZF): 010
+#0002: Memory::::
+#0002: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+#0002: 0000: 1010 0005 2210 0006 8100 FFEC 000A 0000 
+#0004: Register::::
+#0004: GR0:      0 = #0000 = 0000000000000000
+#0004: GR1:    -10 = #FFF6 = 1111111111110110
+#0004: GR2:      0 = #0000 = 0000000000000000
+#0004: GR3:      0 = #0000 = 0000000000000000
+#0004: GR4:      0 = #0000 = 0000000000000000
+#0004: GR5:      0 = #0000 = 0000000000000000
+#0004: GR6:      0 = #0000 = 0000000000000000
+#0004: GR7:      0 = #0000 = 0000000000000000
+#0004: SP:       8 = #0008 = 0000000000001000
+#0004: PR:       4 = #0004 = 0000000000000100
+#0004: FR (OF SF ZF): 010
+#0004: Memory::::
+#0004: adr : 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F
+#0004: 0000: 1010 0005 2210 0006 8100 FFEC 000A 0000